Delay circuits are often used in modern chip and system designs to provide a predetermined delay for an input signal. The delay circuits may be used for a variety of applications, such as sampling clock phase optimization for analog to digital converters.
One example of a known delay circuit utilizes an inverter cell that generates a predetermined delay. Multiple inverter cells may be coupled together in the form of a chain, with the delay from each cell adding up to a required time delay for the entire chain of cells. The inverter delay cell is simple to implement but is very sensitive to process, power supply voltage and ambient temperature variations. Because of the sensitivity of the inverter delay cell, the programmable delay step variation is on the order of 50%. This variation makes the standard inverter delay cell impractical.
In order to reduce the variation, the basic inverter cell has been modified. One modification uses the inverter delay cell 100 as shown in FIG. 1. The inverter delay cell 100 includes an inverter 110, a constant current IIC1, and a capacitor CIC1. The constant current IIC1 is a reference source current that is independent of the process chosen, and thus is not susceptible to process variations. The delay generated by the inverter delay cell 100 is dependent on the constant current LIC1 and the capacitor CIC1. Specifically, in operation, when the input signal to the inverter 110 goes high, the discharge time for the capacitor depends on the constant current IIC1 and the capacitor CIC1.
Another modification to the basic inverter cell is shown in FIG. 2. Rather than receiving a reference source current independent of process, the current for the delay cell 202 is generated by a self-biased current generator 200, thereby reducing variation based on process. However, the self-biased technique still requires complicated calibration to reduce the effects of temperature variation. And, the delay cell 202 is still susceptible to variation based on process. For example, the characteristics of the discharge capacitor CIC2 may still depend on the process variations. Further, as in other delay circuits that rely on multiple, cascaded delay cells, the delay step linearity, sometimes called differential nonlinearity (DNL), may be worse with the increase of delay step due to the accumulation of delay error of each delay cell.
Another type of delay circuit is a delay-locked loop (DLL). Where an accurate reference clock is available, the delay-locked loop may be used to generate the required delay step, the accuracy of which being determined by the reference clock period. However, the DLL design may consume power and area, particularly in the case where the required delay step is quite small compared to the clock period since a long voltage control delay line (VCDL) is needed. Moreover, the accurate reference clock is not always available.
Accordingly, it would be desirable to develop a novel delay circuit which is less sensitive to process, voltage and/or temperature (PVT) variations and small differential nonlinearity.